Non-volatile semiconductor memories (NVSMs) are widely used in many electronic devices such as personal digital assistants (PDAs), laptop computers, mobile phones and digital cameras, among others. Some of these memories have arrays of charge storage transistors, such as floating gate transistors.
A process flow for a vertical gated thyristor or a vertical metal oxide semiconductor (MOS) array includes the following. A first shallow trench isolation (STI) is formed in a first direction. A field oxide is then lowered to a level of silicon and a silicon nitride hard mask is removed. A new silicon nitride layer is deposited, and a second STI is formed in a second direction. The silicon, the silicon nitride and the silicon dioxide are etched at the same time. The trenches are then filled with silicon dioxide and a chemical-mechanical planarization (CMP) landing over the silicon nitride is performed. The silicon dioxide is etched back using a dry etch process. A vertical gate is formed on pillar sidewalls by forming metal spacers. Vertical gate recession, trench filling, CMP, nitride stripping and junction formation then occur. Both the silicon dioxide and the silicon are etched simultaneously to form the second STI trench. Photoresist and/or hard mask consumption will also occur. High aspect ratio pillars are doped from the top. A source region for a vertical MOS or a cathode region for a thyristor are formed by implanting n-type ions at the bottom of the second STI right after etching, and then the species is diffused to dope the bottom portion of the silicon pillars.